Programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs), are user-programmable integrated circuits that can be programmed to implement user-defined logic circuits. In a typical architecture, an FPGA includes an array of configurable logic blocks (CLBs), a collection of programmable input/output blocks (IOBs), and a hierarchy of programmable routing resources for interconnecting the CLBs and IOBs. Additional resources, such as multipliers, memory, and application-specific circuits may also be included. Loading a configuration bitstream into configuration memory cells of the FPGA customizes these CLBs, IOBs, programmable routing resources, and other resources. An exemplary FPGA architecture is described by Young in U.S. Pat. No. 5,933,023, entitled “FPGA Architecture Having RAM Blocks with Programmable Word Length and Width and Dedicated Address and Data Lines,” which is incorporated herein by reference.
PLDs are growing ever larger as vendors attempt to satisfy customer demand for devices capable of performing ever more complex tasks. Unfortunately, as die size increases, so too does the probability of finding a defect on a given die. The process yield therefore decreases with PLD complexity, making already expensive PLDs still more expensive.
PLDs are not design-specific, but instead afford users (e.g., circuit designers) the ability to instantiate an almost unlimited number of circuit variations. Not knowing in advance the purpose to which a given PLD will be dedicated places a heavy burden on the quality and reliability of the PLD because PLD vendors must verify the functionality of any feature that might be used. To avoid disappointing customers, PLD manufacturers discard PLDs that include even relatively minor defects.
PLD defects can be categorized in two general areas: gross defects that render the entire PLD useless or unreliable, and localized defects that affect a relatively small portion of the PLD. Sometimes, for large die, close to two thirds of the die on a given wafer may be discarded because of localized defects. Considering the costs associated with manufacturing large integrated circuits, discarding a large percentage of PLD die has very significant adverse economic impact on PLD manufacturers. In light of this problem, Xilinx, Inc., has developed methods for salvaging some defective PLDs.
Xilinx, Inc., tests defective PLDs to determine their suitability for implementing selected customer designs that may not require the resources impacted by the defects. If the device is found to be unsuitable for one design, the device may be tested for additional designs. These test methods typically employ tests derived from a user design and instantiated on the PLD of interest to verify resources required for the design. The tests allow a PLD vendor to verify the suitability of a device for a given design without requiring the vendor to understand the user design. U.S. patent application Ser. No. 10/104,324 entitled “APPLICATION—SPECIFIC TESTING METHODS FOR PROGRAMMABLE LOGIC DEVICES,” by Robert W. Wells, et al. is incorporated herein by reference. As mentioned in the above-referenced Wells et al. application, once an ASIC candidate is verified for a particular customer design, the PLD manufacturer may want to prevent customers from using the PLD for other designs. The present application details methods and circuits that enable PLD vendors to dedicate PLDs for use with specified designs.